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| author | Sylvain Munaut <tnt@246tNt.com> | 2020-03-20 22:19:55 +0100 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-03-20 22:19:55 +0100 |
| commit | c15ce5a73e94a10e3f9cd4a6961659e27d2ce1a8 (patch) | |
| tree | 2b2c3bd0cb8694a55ad7a37819d5ab24f471dacc | |
| parent | 9b982e929cf9b7a852b7758920cdf7541d0d2cf4 (diff) | |
| download | yosys-c15ce5a73e94a10e3f9cd4a6961659e27d2ce1a8.tar.gz yosys-c15ce5a73e94a10e3f9cd4a6961659e27d2ce1a8.tar.bz2 yosys-c15ce5a73e94a10e3f9cd4a6961659e27d2ce1a8.zip | |
ice40: Fix typos in SPRAM ABC9 timing specs
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index aa1d7aa86..6a0e3031e 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2382,9 +2382,9 @@ module SB_SPRAM256KA ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167 //$setup(negedge STANDBY, posedge CLOCK, 1715); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206 - $setup(WREN, posedge CLK, 289); + $setup(WREN, posedge CLOCK, 289); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222 - (posedge RCLK => (DATAOUT : 16'bx)) = 1821; + (posedge CLOCK => (DATAOUT : 16'bx)) = 1821; // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238 (posedge SLEEP => (DATAOUT : 16'b0)) = 1099; endspecify |