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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-30 17:25:53 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-30 17:25:53 +0200 |
commit | bbf65702a1859d7216f71e1df1193dca6c49cabf (patch) | |
tree | a3fa319809bbaed8a3087833fc08d6affbce47a5 | |
parent | 72e5498bdf12fe841ad0468ea586919965165e36 (diff) | |
download | yosys-bbf65702a1859d7216f71e1df1193dca6c49cabf.tar.gz yosys-bbf65702a1859d7216f71e1df1193dca6c49cabf.tar.bz2 yosys-bbf65702a1859d7216f71e1df1193dca6c49cabf.zip |
Fix valgrind tests when using verific
-rw-r--r-- | frontends/verific/verific.cc | 8 | ||||
-rw-r--r-- | tests/simple/hierdefparam.v | 6 | ||||
-rw-r--r-- | tests/simple/implicit_ports.sv (renamed from tests/simple/implicit_ports.v) | 0 | ||||
-rw-r--r-- | tests/simple/module_scope.v | 8 | ||||
-rw-r--r-- | tests/simple/specify.v | 2 |
5 files changed, 16 insertions, 8 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 185b02e48..b30a5baa0 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2239,11 +2239,15 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par nl_todo.erase(it); } + hier_tree::DeleteHierarchicalTree(); veri_file::Reset(); #ifdef VERIFIC_VHDL_SUPPORT vhdl_file::Reset(); #endif Libset::Reset(); + Message::Reset(); + RuntimeFlags::DeleteAllFlags(); + LineFile::DeleteAllLineFiles(); verific_incdirs.clear(); verific_libdirs.clear(); verific_import_pending = false; @@ -3248,11 +3252,15 @@ struct VerificPass : public Pass { nl_todo.erase(it); } + hier_tree::DeleteHierarchicalTree(); veri_file::Reset(); #ifdef VERIFIC_VHDL_SUPPORT vhdl_file::Reset(); #endif Libset::Reset(); + Message::Reset(); + RuntimeFlags::DeleteAllFlags(); + LineFile::DeleteAllLineFiles(); verific_incdirs.clear(); verific_libdirs.clear(); verific_import_pending = false; diff --git a/tests/simple/hierdefparam.v b/tests/simple/hierdefparam.v index c9368ca7a..a6e0ac1b7 100644 --- a/tests/simple/hierdefparam.v +++ b/tests/simple/hierdefparam.v @@ -1,6 +1,6 @@ `default_nettype none -module hierdefparam_top(input [7:0] A, output [7:0] Y); +module hierdefparam_top(input wire [7:0] A, output wire [7:0] Y); generate begin:foo hierdefparam_a mod_a(.A(A), .Y(Y)); end endgenerate @@ -8,7 +8,7 @@ module hierdefparam_top(input [7:0] A, output [7:0] Y); defparam foo.mod_a.bar[1].mod_b.addvalue = 43; endmodule -module hierdefparam_a(input [7:0] A, output [7:0] Y); +module hierdefparam_a(input wire [7:0] A, output wire [7:0] Y); genvar i; generate for (i = 0; i < 2; i=i+1) begin:bar @@ -19,7 +19,7 @@ module hierdefparam_a(input [7:0] A, output [7:0] Y); assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y; endmodule -module hierdefparam_b(input [7:0] A, output [7:0] Y); +module hierdefparam_b(input wire [7:0] A, output wire [7:0] Y); parameter [7:0] addvalue = 44; assign Y = A + addvalue; endmodule diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.sv index 8b0a6f386..8b0a6f386 100644 --- a/tests/simple/implicit_ports.v +++ b/tests/simple/implicit_ports.sv diff --git a/tests/simple/module_scope.v b/tests/simple/module_scope.v index d07783912..ceeab7311 100644 --- a/tests/simple/module_scope.v +++ b/tests/simple/module_scope.v @@ -3,7 +3,7 @@ module module_scope_Example(o1, o2); parameter [31:0] v1 = 10; parameter [31:0] v2 = 20; - output [31:0] o1, o2; + output wire [31:0] o1, o2; assign module_scope_Example.o1 = module_scope_Example.v1; assign module_scope_Example.o2 = module_scope_Example.v2; endmodule @@ -11,14 +11,14 @@ endmodule module module_scope_ExampleLong(o1, o2); parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10; parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20; - output [31:0] o1, o2; + output wire [31:0] o1, o2; assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1; assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2; endmodule module module_scope_top( - output [31:0] a1, a2, b1, b2, c1, c2, - output [31:0] d1, d2, e1, e2, f1, f2 + output wire [31:0] a1, a2, b1, b2, c1, c2, + output wire [31:0] d1, d2, e1, e2, f1, f2 ); module_scope_Example a(a1, a2); module_scope_Example #(1) b(b1, b2); diff --git a/tests/simple/specify.v b/tests/simple/specify.v index f19418d90..2c784ef6d 100644 --- a/tests/simple/specify.v +++ b/tests/simple/specify.v @@ -1,4 +1,4 @@ -module test_specify; +module test_specify(input A, output B); specparam a=1; |