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authorEddie Hung <eddie@fpgeh.com>2019-06-21 12:13:00 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-21 12:13:00 -0700
commitae8305ffcc0c812488163bcc35365d473ce1345d (patch)
treed44b75e5fb3a5520070bc9d41d3f41778003c2af
parent15535112b7b4caa1da75274397c5a3ba885a7349 (diff)
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Fix testcase
-rw-r--r--tests/various/muxpack.ys7
1 files changed, 4 insertions, 3 deletions
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index ef8a6dab9..de5eec87f 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -230,13 +230,14 @@ sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_overlap
-prep
+#prep # Do not prep otherwise $pmux's overlapping entry will get removed
+proc
design -save gold
muxpack
-#opt # Do not opt otherwise $pmux's overlapping entry will get removed
+opt
stat
select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
+select -assert-count 2 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate