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author | Clifford Wolf <clifford@clifford.at> | 2014-10-30 09:12:55 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-10-30 09:12:55 +0100 |
commit | ac8f4d298b3cc351fa0658857e11069a67adb7ba (patch) | |
tree | cbb74baa3a8f0302de4dc4d2d849990eb6434cfb | |
parent | 269e37e969562275f337362b5423e2801f9c5765 (diff) | |
download | yosys-ac8f4d298b3cc351fa0658857e11069a67adb7ba.tar.gz yosys-ac8f4d298b3cc351fa0658857e11069a67adb7ba.tar.bz2 yosys-ac8f4d298b3cc351fa0658857e11069a67adb7ba.zip |
Improved nomem2reg documentation
-rw-r--r-- | README | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -248,7 +248,10 @@ Verilog Attributes and non-standard features is strongly recommended instead). - The "nomem2reg" attribute on modules or arrays prohibits the - automatic early conversion of arrays to separate registers. + automatic early conversion of arrays to separate registers. This + is potentially dangerous. Usually the front-end has good reasons + for converting an array to a list of registers. Prohibiting this + step will likely result in incorrect synthesis results. - The "mem2reg" attribute on modules or arrays forces the early conversion of arrays to separate registers. |