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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 15:47:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 15:47:36 -0700 |
| commit | aa1491add3722e4cfae35755cc4cecfd3e5a6c82 (patch) | |
| tree | a96c174ea9b6d729eba67c12cb0c798d031ae25e | |
| parent | ba629e6a288e0445c648623c2aeae194d41752fd (diff) | |
| download | yosys-aa1491add3722e4cfae35755cc4cecfd3e5a6c82.tar.gz yosys-aa1491add3722e4cfae35755cc4cecfd3e5a6c82.tar.bz2 yosys-aa1491add3722e4cfae35755cc4cecfd3e5a6c82.zip | |
Resolve TODO with pin assignments for SRL*
| -rw-r--r-- | techlibs/xilinx/abc_map.v | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index c3701b1a8..0c85d6656 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -101,8 +101,7 @@ module SRL16E ( .Q(\$Q ), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D) ); - // TODO: Check if SRL uses fast inputs or slow inputs - \$__ABC_LUT6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q)); + \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q)); endmodule module SRLC32E ( @@ -120,6 +119,5 @@ module SRLC32E ( .Q(\$Q ), .Q31(Q31), .A(A), .CE(CE), .CLK(CLK), .D(D) ); - // TODO: Check if SRL uses fast inputs or slow inputs - \$__ABC_LUT6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q)); + \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q)); endmodule |