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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-23 19:13:45 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-05-23 19:13:45 +0200 |
| commit | a6ec5754c6c2be6877904569b644ad8eae4aac1c (patch) | |
| tree | 3d1452f38ce06bf5129b5fcdd592b6515c72a918 | |
| parent | e47cfe277e86d27c28c60d82464f0aec4ebc044b (diff) | |
| download | yosys-a6ec5754c6c2be6877904569b644ad8eae4aac1c.tar.gz yosys-a6ec5754c6c2be6877904569b644ad8eae4aac1c.tar.bz2 yosys-a6ec5754c6c2be6877904569b644ad8eae4aac1c.zip | |
Use analysis mode if set in file
| -rw-r--r-- | frontends/verific/verific.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b130edbdc..29131fdc5 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2717,7 +2717,7 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { - unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific + unsigned verilog_mode = veri_file::UNDEFINED; bool is_formal = false; const char* filename = nullptr; @@ -2764,7 +2764,7 @@ struct VerificPass : public Pass { veri_file::DefineMacro("VERIFIC"); veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS"); - if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) { + if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } |