diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:31:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:31:55 -0700 |
| commit | a45c09c8d1320d311fbda8d615d39117acb8f70b (patch) | |
| tree | 7f2442886fbc77130d440fe6ab98a6223acf91a9 | |
| parent | 1b08f861b6f95dba561ec48f71d3ab5bc18f64f2 (diff) | |
| download | yosys-a45c09c8d1320d311fbda8d615d39117acb8f70b.tar.gz yosys-a45c09c8d1320d311fbda8d615d39117acb8f70b.tar.bz2 yosys-a45c09c8d1320d311fbda8d615d39117acb8f70b.zip | |
Account for D port being a constant
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 45d44247a..b18119b87 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -105,7 +105,7 @@ endcode match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->has_keep_attr() - select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index <IdString> next->type === first->type index <SigBit> port(next, \Q) === port(first, \D) @@ -132,7 +132,7 @@ match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->has_keep_attr() - select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index <IdString> next->type === chain.back()->type index <SigBit> port(next, \Q) === port(chain.back(), \D) @@ -201,7 +201,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() - select !port(first, \Q)[0].wire->get_bool_attribute(\keep) + select port(first, \Q)[0].wire && !port(first, \Q)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(first, \Q)) select nusers(port(first, \Q)[idx]) <= 2 index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] @@ -272,7 +272,7 @@ match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !next->has_keep_attr() - select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(next, \Q)) select nusers(port(next, \Q)[idx]) <= 3 index <IdString> next->type === chain.back().first->type |