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authorEddie Hung <eddie@fpgeh.com>2020-01-13 19:22:23 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-13 19:22:23 -0800
commita2c4d98da70744253ccbe253083ef9df5fa39305 (patch)
tree82972932412d06a5bdb0203b46bb80c8598532d5
parenta6d4ea74634826741f09793c36d596f2fa239f62 (diff)
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abc9: add -run option
-rw-r--r--passes/techmap/abc9.cc15
1 files changed, 14 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2e3df773e..2627ab9ca 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -91,6 +91,11 @@ struct Abc9Pass : public ScriptPass
log("tool [1] for technology mapping of the current design to a target FPGA\n");
log("architecture. Only fully-selected modules are supported.\n");
log("\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
log(" -exe <command>\n");
#ifdef ABCEXTERNAL
log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
@@ -210,13 +215,21 @@ struct Abc9Pass : public ScriptPass
}
if (arg == "-dff") {
dff_mode = true;
- exe_cmd << " " << arg;
+ exe_cmd << " " << arg;
continue;
}
if (arg == "-nocleanup") {
cleanup = false;
continue;
}
+ if (arg == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ continue;
+ }
break;
}
extra_args(args, argidx, design);