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| author | Clifford Wolf <clifford@clifford.at> | 2018-01-09 18:42:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-01-09 18:42:19 +0100 |
| commit | 9ac560f5d3e5847b7e475195f66b7034e91fd938 (patch) | |
| tree | 17c0a0dbc2cd845523b52d27c6c1caf215578b69 | |
| parent | a96c775a7301645b27486a5e663c75fca460f577 (diff) | |
| download | yosys-9ac560f5d3e5847b7e475195f66b7034e91fd938.tar.gz yosys-9ac560f5d3e5847b7e475195f66b7034e91fd938.tar.bz2 yosys-9ac560f5d3e5847b7e475195f66b7034e91fd938.zip | |
Add "dffinit -highlow" and fix synth_intel
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | passes/techmap/dffinit.cc | 20 | ||||
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 2 |
2 files changed, 21 insertions, 1 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index d737b3424..6a8a86383 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -38,15 +38,25 @@ struct DffinitPass : public Pass { log(" operate on the specified cell type. this option can be used\n"); log(" multiple times.\n"); log("\n"); + log(" -highlow\n"); + log(" use the string values \"high\" and \"low\" to represent a single-bit\n"); + log(" initial value of 1 or 0. (multi-bit values are not supported in this\n"); + log(" mode.)\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n"); dict<IdString, dict<IdString, IdString>> ff_types; + bool highlow_mode = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-highlow") { + highlow_mode = true; + continue; + } if (args[argidx] == "-ff" && argidx+3 < args.size()) { IdString cell_name = RTLIL::escape_id(args[++argidx]); IdString output_port = RTLIL::escape_id(args[++argidx]); @@ -106,6 +116,16 @@ struct DffinitPass : public Pass { cleanup_bits.insert(sig[i]); } + if (highlow_mode && GetSize(value) != 0) { + if (GetSize(value) != 1) + log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n", + log_id(module), log_id(cell), log_id(it.second)); + if (value[0] == State::S1) + value = Const("high"); + else + value = Const("low"); + } + log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second), log_id(it.first), log_signal(sig), log_signal(value)); cell->setParam(it.second, value); diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9b3e92b14..9e632c861 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -219,7 +219,7 @@ struct SynthIntelPass : public ScriptPass { run("techmap -map +/intel/cycloneiv/cells_map.v"); else run("techmap -map +/intel/cycloneive/cells_map.v"); - run("dffinit -ff dffeas Q INIT"); + run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); } |