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| author | Clifford Wolf <clifford@clifford.at> | 2013-02-27 10:36:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-02-27 10:36:17 +0100 |
| commit | 99d73fe0280ab41a1d6e75ef0b9a0117455838f9 (patch) | |
| tree | fc2884c2ee0b77bcbf24ead19da907ef8b36d13b | |
| parent | a77a5136af2cd4df07972db9cb0bfc65eec90715 (diff) | |
| download | yosys-99d73fe0280ab41a1d6e75ef0b9a0117455838f9.tar.gz yosys-99d73fe0280ab41a1d6e75ef0b9a0117455838f9.tar.bz2 yosys-99d73fe0280ab41a1d6e75ef0b9a0117455838f9.zip | |
Added some additional TODO items
| -rw-r--r-- | README | 8 |
1 files changed, 6 insertions, 2 deletions
@@ -153,9 +153,9 @@ for them: - The "tri", "triand", "trior", "wand" and "wor" net types -- The "library" and "configuration" source file formats +- The "config" keyword and library map files -- The "disable" and "primitive" statements +- The "disable", "primitive" and "specify" statements - Latched logic (is synthesized as logic with feedback loops) @@ -196,7 +196,11 @@ TODOs / Open Bugs - Implement missing Verilog 2005 features: - Signed constants + - Constant functions + - Indexed part selects + - Multi-dimensional arrays - ROM modelling using "initial" blocks + - The "defparam <cell_name>.<parameter_name> = <value>;" syntax - Builtin primitive gates (and, nand, cmos, nmos, pmos, etc..) - Ignore what needs to be ignored (e.g. drive and charge strenghts) - Check standard vs. implementation to identify missing features |