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author | Jannis Harder <me@jix.one> | 2022-12-09 15:22:21 +0100 |
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committer | Jannis Harder <me@jix.one> | 2022-12-09 15:25:40 +0100 |
commit | 967529abb1dc13a3bf220f2a7ec6ad12dd8ce7ce (patch) | |
tree | ea03d67333296cfca77490e77cc1eabc5f676f26 | |
parent | 7ad7b550cb1157fb4c5c901006a700cb10d0e722 (diff) | |
download | yosys-967529abb1dc13a3bf220f2a7ec6ad12dd8ce7ce.tar.gz yosys-967529abb1dc13a3bf220f2a7ec6ad12dd8ce7ce.tar.bz2 yosys-967529abb1dc13a3bf220f2a7ec6ad12dd8ce7ce.zip |
formalff: Proper error messages on async inputs for the -clk2ff mode
-rw-r--r-- | passes/sat/formalff.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index 209486a37..962e350a1 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -479,6 +479,9 @@ struct FormalFfPass : public Pass { if (ff.sig_clk.is_fully_const()) log_error("Const CLK on %s (%s) from module %s, run async2sync first.\n", log_id(cell), log_id(cell->type), log_id(module)); + if (ff.has_aload || ff.has_arst || ff.has_sr) + log_error("Async inputs on %s (%s) from module %s, run async2sync first.\n", + log_id(cell), log_id(cell->type), log_id(module)); auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr; |