diff options
author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-30 20:30:25 -0700 |
---|---|---|
committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-30 20:30:25 -0700 |
commit | 94a6923e7dd363c5b11116e9bd85aa012fed512a (patch) | |
tree | 87c4fdee2b95b278d8a2caa7ec017bf2a7588d0a | |
parent | dd7204c0bdb65956fdf27925da3ccfe6f592d012 (diff) | |
download | yosys-94a6923e7dd363c5b11116e9bd85aa012fed512a.tar.gz yosys-94a6923e7dd363c5b11116e9bd85aa012fed512a.tar.bz2 yosys-94a6923e7dd363c5b11116e9bd85aa012fed512a.zip |
Updated tech lib for greenpak4 counter with some clarifications
-rw-r--r-- | techlibs/greenpak4/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6e3003f5e..2727d9246 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -99,8 +99,8 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT); OUT <= (count == 8'h0); end - //datasheet is unclear but experimental testing confirms that POR value is COUNT_TO. - //Reset value is clearly 0 except in count/FSM cells where it's configurable. + //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm. + //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now. //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues... always @(posedge CLK) begin @@ -114,7 +114,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT); count <= 0; if((RESET_MODE == "FALLING") && !RST) count <= 0; - if((RESET_MODE == "BITH") && RST) + if((RESET_MODE == "BOTH") && RST) count <= 0; */ end |