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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-24 14:12:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-24 14:12:50 +0200 |
| commit | 914ae3401eb9c05564391b5f0d3b6fc069f7cbc0 (patch) | |
| tree | 4f705eb44b1574e13a169ffbaca836e4a3fa4a6e | |
| parent | c6ca4780e2c5cf22863a943e1dfa88bd7b690784 (diff) | |
| download | yosys-914ae3401eb9c05564391b5f0d3b6fc069f7cbc0.tar.gz yosys-914ae3401eb9c05564391b5f0d3b6fc069f7cbc0.tar.bz2 yosys-914ae3401eb9c05564391b5f0d3b6fc069f7cbc0.zip | |
Improved $adff simplification
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index d2695b167..24c2d3fa3 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -147,7 +147,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) goto delete_dff; } - if (sig_d.is_fully_const() && !sig_r.size() && (!has_init || val_init == sig_d.as_const())) { + if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { RTLIL::SigSig conn(sig_q, sig_d); mod->connect(conn); goto delete_dff; |