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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-23 23:16:43 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-23 23:16:43 +0200 |
| commit | 8f12c5b063a458ac5f751f54651baebd84006307 (patch) | |
| tree | dfc90dd81bb00a29a48f263067fa0672b4928bd0 | |
| parent | 2a59cd9ed0c6d4ddf19fc735682fa236018bcf2c (diff) | |
| download | yosys-8f12c5b063a458ac5f751f54651baebd84006307.tar.gz yosys-8f12c5b063a458ac5f751f54651baebd84006307.tar.bz2 yosys-8f12c5b063a458ac5f751f54651baebd84006307.zip | |
simplemap: Fix $dffsre mapping.
| -rw-r--r-- | passes/techmap/simplemap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index c8388e2d7..b9d337da4 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -489,7 +489,7 @@ void simplemap_dffsre(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_d = cell->getPort(ID::D); RTLIL::SigSpec sig_q = cell->getPort(ID::Q); - IdString gate_type = stringf("$_DFFSR_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol); + IdString gate_type = stringf("$_DFFSRE_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); |