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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 20:31:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 20:31:56 -0700 |
| commit | 8d18c256f0d6fee25fe7a55ed7d882c478465b09 (patch) | |
| tree | b556f634590b8310d8ea90f6f37fd2f087a78b73 | |
| parent | 1abe93e48d8bb78cd0753d46dfbe1885a1e803eb (diff) | |
| parent | fb8fab4a29e5a3978cadf2b1bd8920b772150028 (diff) | |
| download | yosys-8d18c256f0d6fee25fe7a55ed7d882c478465b09.tar.gz yosys-8d18c256f0d6fee25fe7a55ed7d882c478465b09.tar.bz2 yosys-8d18c256f0d6fee25fe7a55ed7d882c478465b09.zip | |
Merge branch 'master' into xaig
| -rw-r--r-- | CHANGELOG | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -18,11 +18,13 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "equiv_opt" pass - Added "shregmap -tech xilinx" - Added "read_aiger" frontend + - Added "muxcover -mux{4,8,16}=<cost>" + - Added "muxcover -dmux=<cost>" + - Added "muxcover -nopartial" - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) - - Extended "muxcover -mux{4,8,16}=<cost>" - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Fixed sign extension of unsized constants with 'bx and 'bz MSB |