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| author | Lofty <dan.ravensloft@gmail.com> | 2023-01-25 09:26:58 +0000 |
|---|---|---|
| committer | Lofty <dan.ravensloft@gmail.com> | 2023-01-26 05:19:45 +0000 |
| commit | 822c7b0341064c3d0d9b142dc6ce61c66797159a (patch) | |
| tree | ed079cb45f41e4f3615138bcd84c785dab69686f | |
| parent | 2e3c08adc41a8d1cc1ac383d3b048204a691672a (diff) | |
| download | yosys-822c7b0341064c3d0d9b142dc6ce61c66797159a.tar.gz yosys-822c7b0341064c3d0d9b142dc6ce61c66797159a.tar.bz2 yosys-822c7b0341064c3d0d9b142dc6ce61c66797159a.zip | |
muxcover: do not add decode muxes with x inputs
| -rw-r--r-- | passes/techmap/muxcover.cc | 5 | ||||
| -rw-r--r-- | tests/various/muxcover.ys | 40 |
2 files changed, 41 insertions, 4 deletions
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index a90d81985..2656f30ce 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -179,7 +179,7 @@ struct MuxcoverWorker int prepare_decode_mux(SigBit &A, SigBit B, SigBit sel, SigBit bit) { - if (A == B || sel == State::Sx) + if (A == B || A == State::Sx || B == State::Sx || sel == State::Sx) return 0; tuple<SigBit, SigBit, SigBit> key(A, B, sel); @@ -197,9 +197,6 @@ struct MuxcoverWorker if (std::get<2>(entry)) return 0; - if (A == State::Sx || B == State::Sx) - return 0; - return cost_dmux / GetSize(std::get<1>(entry)); } diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index 67e9625e6..37a90dcb0 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -508,3 +508,43 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter sat -verify -prove-asserts -show-ports miter + +## implement a mux6 as a mux8 :: https://github.com/YosysHQ/yosys/issues/3591 + +design -reset +read_verilog << EOF +module test (A, S, Y); + parameter INPUTS = 6; + + input [INPUTS-1:0] A; + input [$clog2(INPUTS)-1:0] S; + + wire [15:0] AA = {{(16-INPUTS){1'b0}}, A}; + wire [3:0] SS = {{(4-$clog2(INPUTS)){1'b0}}, S}; + + output Y = SS[3] ? (SS[2] ? SS[1] ? (SS[0] ? AA[15] : AA[14]) + : (SS[0] ? AA[13] : AA[12]) + : SS[1] ? (SS[0] ? AA[11] : AA[10]) + : (SS[0] ? AA[9] : AA[8])) + : (SS[2] ? SS[1] ? (SS[0] ? AA[7] : AA[6]) + : (SS[0] ? AA[5] : AA[4]) + : SS[1] ? (SS[0] ? AA[3] : AA[2]) + : (SS[0] ? AA[1] : AA[0])); +endmodule +EOF + +prep +design -save gold +simplemap t:\$mux +muxcover +opt_clean -purge +select -assert-count 1 t:$_MUX8_ +select -assert-none t:$_MUX8_ %% t:* %D +techmap -map +/simcells.v t:$_MUX8_ +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter +sat -verify -prove-asserts -show-ports miter |