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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-19 15:15:50 -0800 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-19 15:15:50 -0800 |
commit | 7b026c4bc316a44f2722cd4ddc96b4da1d1458b6 (patch) | |
tree | eeed98c796610c06d41ffc276963b6721a67db47 | |
parent | d304882cba32cc9eb9be163fe6f24211bd39594a (diff) | |
download | yosys-7b026c4bc316a44f2722cd4ddc96b4da1d1458b6.tar.gz yosys-7b026c4bc316a44f2722cd4ddc96b4da1d1458b6.tar.bz2 yosys-7b026c4bc316a44f2722cd4ddc96b4da1d1458b6.zip |
Same for ascii AIGERs too
-rw-r--r-- | frontends/aiger/aigerparse.cc | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 941899316..2219eedb1 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -527,12 +527,19 @@ void AigerReader::parse_aiger_ascii() } else { log_debug("%d is an output\n", l1); - wire = createWireIfNotExists(module, l1); - } - if (wire->port_input) { - RTLIL::Wire *new_wire = module->addWire(NEW_ID); - module->connect(new_wire, wire); - wire = new_wire; + const unsigned variable = l1 >> 1; + const bool invert = l1 & 1; + RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix? + wire = module->wire(wire_name); + if (!wire) + wire = createWireIfNotExists(module, l1); + else { + if ((wire->port_input || wire->port_output)) { + RTLIL::Wire *new_wire = module->addWire(stringf("\\o%zu", outputs.size())); + module->connect(new_wire, wire); + wire = new_wire; + } + } } wire->port_output = true; outputs.push_back(wire); |