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| author | whitequark <whitequark@whitequark.org> | 2020-06-29 12:34:09 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-29 12:34:09 +0000 |
| commit | 7860fb628f76c82bf30f6847809d8a8f79a4ff00 (patch) | |
| tree | 79f92ea77bb1eaf9905bbad944918e45ada95598 | |
| parent | b822beb1b2e667459f4864b759b7f4d82a064354 (diff) | |
| parent | e2cfe57eddce6708ca67692131dc7e7f89bdd049 (diff) | |
| download | yosys-7860fb628f76c82bf30f6847809d8a8f79a4ff00.tar.gz yosys-7860fb628f76c82bf30f6847809d8a8f79a4ff00.tar.bz2 yosys-7860fb628f76c82bf30f6847809d8a8f79a4ff00.zip | |
Merge pull request #2197 from Xiretza/test_cell-shifts
test_cell: don't generate directional shifts with \B_SIGNED=1
| -rw-r--r-- | passes/tests/test_cell.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 942468e29..125efbaa3 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -264,6 +264,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort(ID::Y, wire); } + if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { + cell->parameters[ID::B_SIGNED] = false; + } + if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); |