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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:53:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:53:08 -0800 |
| commit | 7347c13071c1d8ab9ac5130c607db08725f91edc (patch) | |
| tree | 1ed71f3671e5e7f8ad4b06c23ee4e7ab41e26652 | |
| parent | cf3a13746d27fee141700e2c6ea40d528267190f (diff) | |
| parent | 5c89dead5f481edaccd46ebc0af907544c89654f (diff) | |
| download | yosys-7347c13071c1d8ab9ac5130c607db08725f91edc.tar.gz yosys-7347c13071c1d8ab9ac5130c607db08725f91edc.tar.bz2 yosys-7347c13071c1d8ab9ac5130c607db08725f91edc.zip | |
Merge branch 'master' into eddie/abc9_refactor
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index abe4962d5..22dca3c47 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2396,8 +2396,8 @@ module DSP48E1 ( if (CEB2) Br2 <= Br1; end end else if (BREG == 1) begin - //initial Br1 = 25'b0; - initial Br2 = 25'b0; + //initial Br1 = 18'b0; + initial Br2 = 18'b0; always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; @@ -2444,7 +2444,7 @@ module DSP48E1 ( endgenerate // A/D input selection and pre-adder - wire signed [29:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; + wire signed [24:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); |