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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-27 12:15:42 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-27 12:15:42 +0100 |
| commit | 6f26695d9b596fe3b221334a93c5d94678582aea (patch) | |
| tree | 9e55368e7f4707b727290b0c46a901f0e3690a62 | |
| parent | b6fbeb0969773770af79fe4bd8f5b15c863ef90b (diff) | |
| download | yosys-6f26695d9b596fe3b221334a93c5d94678582aea.tar.gz yosys-6f26695d9b596fe3b221334a93c5d94678582aea.tar.bz2 yosys-6f26695d9b596fe3b221334a93c5d94678582aea.zip | |
Add -lz for verific builds
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -281,7 +281,7 @@ ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib_eval VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC -LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) +LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -lz endif ifeq ($(ENABLE_COVER),1) |