Add Xilinx RAM64X1D and RAM128X1D simulation models

4 files changed, 30 insertions, 23 deletions

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index d4d4bd09a..887ea27d9 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -27,7 +27,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v))
 
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1f114a22c..eba17ac9c 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -156,3 +156,33 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
+module RAM64X1D (
+  output DPO, SPO,
+  input  D, WCLK, WE,
+  input  A0, A1, A2, A3, A4, A5,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+  parameter INIT = 64'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire [5:0] a = {A5, A4, A3, A2, A1, A0};
+  wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+  reg [63:0] mem = INIT;
+  assign SPO = mem[a];
+  assign DPO = mem[dpra];
+  wire clk = WCLK ^ IS_WCLK_INVERTED;
+  always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM128X1D (
+  output       DPO, SPO,
+  input        D, WCLK, WE,
+  input  [6:0] A, DPRA
+);
+  parameter INIT = 128'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  reg [127:0] mem = INIT;
+  assign SPO = mem[A];
+  assign DPO = mem[DPRA];
+  wire clk = WCLK ^ IS_WCLK_INVERTED;
+  always @(posedge clk) if (WE) mem[A] <= D;
+endmodule
diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v
deleted file mode 100644
index 11168fe13..000000000
--- a/techlibs/xilinx/drams_bb.v
+++ /dev/null
@@ -1,20 +0,0 @@
-
-module RAM64X1D (
-	output DPO, SPO,
-	input  D, WCLK, WE,
-	input  A0, A1, A2, A3, A4, A5,
-	input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
-	parameter INIT = 64'h0;
-	parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
-module RAM128X1D (
-	output       DPO, SPO,
-	input        D, WCLK, WE,
-	input  [6:0] A, DPRA
-);
-	parameter INIT = 128'h0;
-	parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e7ec1e6e8..b60295ac0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -71,7 +71,6 @@ struct SynthXilinxPass : public Pass {
 		log("        read_verilog -lib +/xilinx/cells_sim.v\n");
 		log("        read_verilog -lib +/xilinx/cells_xtra.v\n");
 		log("        read_verilog -lib +/xilinx/brams_bb.v\n");
-		log("        read_verilog -lib +/xilinx/drams_bb.v\n");
 		log("        hierarchy -check -top <top>\n");
 		log("\n");
 		log("    flatten:     (only if -flatten)\n");
@@ -168,7 +167,6 @@ struct SynthXilinxPass : public Pass {
 			Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
 			Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 			Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
-			Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v");
 			Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 		}