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| author | David Shah <dave@ds0.me> | 2020-03-15 17:16:57 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-15 17:16:57 +0000 |
| commit | 685392fed88db3df3dbc077f3d52fb0b4ae36c45 (patch) | |
| tree | bc17453fc9765b02c53dbc4a2fcc8aef55fafb7a | |
| parent | acb341745d436987ad764c9198ff0c6ab63c572c (diff) | |
| parent | acd9eeef7c85f1bd72f42d86bb634769556a04c6 (diff) | |
| download | yosys-685392fed88db3df3dbc077f3d52fb0b4ae36c45.tar.gz yosys-685392fed88db3df3dbc077f3d52fb0b4ae36c45.tar.bz2 yosys-685392fed88db3df3dbc077f3d52fb0b4ae36c45.zip | |
Merge pull request #1773 from smunaut/fix_spram_model
ice40: Fix SPRAM model to keep data stable if chipselect is low
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 17fe2ec99..aa1d7aa86 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2350,16 +2350,19 @@ module SB_SPRAM256KA ( if (off) begin DATAOUT <= 0; end else - if (CHIPSELECT && !STANDBY && !WREN) begin - DATAOUT <= mem[ADDRESS]; - end else begin - if (CHIPSELECT && !STANDBY && WREN) begin + if (STANDBY) begin + DATAOUT <= 'bx; + end else + if (CHIPSELECT) begin + if (!WREN) begin + DATAOUT <= mem[ADDRESS]; + end else begin if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0]; if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4]; if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8]; if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12]; + DATAOUT <= 'bx; end - DATAOUT <= 'bx; end end `endif |