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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-15 13:16:08 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-15 13:16:08 +0100 |
| commit | 67effc9f5bc82b45ff163bfefea53c40d2c8819a (patch) | |
| tree | 9d840a0f9d5d3f52c98316622d08999022f471da | |
| parent | 4440610d3ffc5426c38e5cf8fccd757203c11a0e (diff) | |
| download | yosys-67effc9f5bc82b45ff163bfefea53c40d2c8819a.tar.gz yosys-67effc9f5bc82b45ff163bfefea53c40d2c8819a.tar.bz2 yosys-67effc9f5bc82b45ff163bfefea53c40d2c8819a.zip | |
Fixed opt_const handling of double invert with non-1 output width
| -rw-r--r-- | passes/opt/opt_const.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 34d1a69c1..f611d7211 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -108,7 +108,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons #define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) #define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_)) - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].width == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); goto next_cell; |