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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 14:44:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 14:44:08 -0700 |
| commit | 671cca59a9f63f9fb7102727eb4dee1b18fe3ef6 (patch) | |
| tree | 813b69aa4f1a2f4d1a9446f8b50ebaee34ea20ce | |
| parent | 1ec5f18346dd3f50e2340f4b79239a045ce7dd72 (diff) | |
| download | yosys-671cca59a9f63f9fb7102727eb4dee1b18fe3ef6.tar.gz yosys-671cca59a9f63f9fb7102727eb4dee1b18fe3ef6.tar.bz2 yosys-671cca59a9f63f9fb7102727eb4dee1b18fe3ef6.zip | |
Missing abc_flop_q attribute on SPRAM
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index cf7b9d252..70cd51ed1 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -887,7 +887,7 @@ module SB_SPRAM256KA ( input [15:0] DATAIN, input [3:0] MASKWREN, input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF, - output reg [15:0] DATAOUT + (* abc_flop_q *) output reg [15:0] DATAOUT ); `ifndef BLACKBOX `ifndef EQUIV |