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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 10:47:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 10:47:14 -0700 |
| commit | 659c04a68d15b20a9421ea5d154b259265f39494 (patch) | |
| tree | 274f4383a1a620973953a6e8410715fb445b2dd6 | |
| parent | 699d8e393953a3e5f0c35afec54464e6810f8f1d (diff) | |
| download | yosys-659c04a68d15b20a9421ea5d154b259265f39494.tar.gz yosys-659c04a68d15b20a9421ea5d154b259265f39494.tar.bz2 yosys-659c04a68d15b20a9421ea5d154b259265f39494.zip | |
Update abc_box_id numbering
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index e95602ab2..9f6f9c47e 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -23,7 +23,7 @@ module \$__ABC_FF_ (input C, D, output Q); endmodule -(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *) +(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *) module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ ); parameter [0:0] INIT = 1'b0; //parameter [0:0] IS_C_INVERTED = 1'b0; diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index bb9258e78..633e2d484 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -54,20 +54,20 @@ RAM128X1D 6 0 17 2 # Inputs: C CE D R \$pastQ # Outputs: Q -FDRE 6 1 5 1 +FDRE 7 1 5 1 - 109 -46 358 0 # Inputs: C CE D S \$pastQ # Outputs: Q -FDSE 7 0 5 1 +FDSE 8 0 5 1 - 109 -46 358 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE 8 0 5 1 +FDCE 9 0 5 1 - 109 - -46 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q -FDPE 9 0 5 1 +FDPE 10 0 5 1 - 109 -46 - 0 |