Merge pull request #3277 from YosysHQ/lofty/rename-scramble_name

2 files changed, 87 insertions, 0 deletions

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 81da35ffe..b49d5cdc2 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -20,6 +20,7 @@
 #include "kernel/register.h"
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
+#include "kernel/hashlib.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -156,6 +157,13 @@ struct RenamePass : public Pass {
 		log("\n");
 		log("Rename top module.\n");
 		log("\n");
+		log("\n");
+		log("    rename -scramble-name [-seed <seed>] [selection]\n");
+		log("\n");
+		log("Assign randomly-generated names to all selected wires and cells. The seed option\n");
+		log("can be used to change the random number generator seed from the default, but it\n");
+		log("must be non-zero.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -167,7 +175,9 @@ struct RenamePass : public Pass {
 		bool flag_hide = false;
 		bool flag_top = false;
 		bool flag_output = false;
+		bool flag_scramble_name = false;
 		bool got_mode = false;
+		unsigned int seed = 1;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -203,6 +213,11 @@ struct RenamePass : public Pass {
 				got_mode = true;
 				continue;
 			}
+			if (arg == "-scramble-name" && !got_mode) {
+				flag_scramble_name = true;
+				got_mode = true;
+				continue;
+			}
 			if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
 				int pos = args[++argidx].find('%');
 				pattern_prefix = args[argidx].substr(0, pos);
@@ -211,6 +226,11 @@ struct RenamePass : public Pass {
 			}
 			if (arg == "-suffix" && argidx + 1 < args.size()) {
 				cell_suffix = args[++argidx];
+				continue;
+			}
+			if (arg == "-seed" && argidx+1 < args.size()) {
+				seed = std::stoi(args[++argidx]);
+				continue;
 			}
 			break;
 		}
@@ -329,6 +349,42 @@ struct RenamePass : public Pass {
 			design->rename(module, new_name);
 		}
 		else
+		if (flag_scramble_name)
+		{
+			extra_args(args, argidx, design);
+
+			if (seed == 0)
+				log_error("Seed for -scramble-name cannot be zero.\n");
+
+			for (auto module : design->selected_modules())
+			{
+				if (module->memories.size() != 0 || module->processes.size() != 0) {
+					log_warning("Skipping module %s with unprocessed memories or processes\n", log_id(module));
+					continue;
+				}
+
+				dict<RTLIL::Wire *, IdString> new_wire_names;
+				dict<RTLIL::Cell *, IdString> new_cell_names;
+
+				for (auto wire : module->selected_wires())
+					if (wire->port_id == 0) {
+						seed = mkhash_xorshift(seed);
+						new_wire_names[wire] = stringf("$_%u_", seed);
+					}
+
+				for (auto cell : module->selected_cells()) {
+					seed = mkhash_xorshift(seed);
+					new_cell_names[cell] = stringf("$_%u_", seed);
+				}
+
+				for (auto &it : new_wire_names)
+					module->rename(it.first, it.second);
+
+				for (auto &it : new_cell_names)
+					module->rename(it.first, it.second);
+			}
+		}
+		else
 		{
 			if (argidx+2 != args.size())
 				log_cmd_error("Invalid number of arguments!\n");
diff --git a/tests/various/rename_scramble_name.ys b/tests/various/rename_scramble_name.ys
new file mode 100644
index 000000000..9a36d0922
--- /dev/null
+++ b/tests/various/rename_scramble_name.ys
@@ -0,0 +1,31 @@
+read_verilog <<EOF
+module top();
+    wire a, b, c;
+endmodule
+EOF
+
+proc
+hierarchy -top top
+rename -seed 2 -scramble-name w:*
+select -assert-none w:a w:b w:c
+select -assert-count 3 w:$_*_
+select -assert-none w:$_*_ %% %n
+design -reset
+
+read_verilog <<EOF
+module foo(input a, b, output c);
+    assign c = a + b;
+endmodule
+
+module top();
+    wire a, b, c;
+    foo bar(.a(a), .b(b), .c(c));
+endmodule
+EOF
+
+proc
+hierarchy -top top
+rename -seed 2 -scramble-name c:bar
+select -assert-none c:bar
+select -assert-count 1 c:$_*_
+select -assert-none c:$_*_ w:* foo/c:$add$<<EOF:2$1 %% %n