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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-29 17:24:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-29 17:24:25 -0700 |
| commit | 5d16bf831688ff665b0ec2abd6835b71320b2db5 (patch) | |
| tree | f7bbb34a49a5da5aeeb89aa99b2d5731d626326e | |
| parent | 18cabe9370c46b72e9fb52eb9be5a7c7fb873274 (diff) | |
| download | yosys-5d16bf831688ff665b0ec2abd6835b71320b2db5.tar.gz yosys-5d16bf831688ff665b0ec2abd6835b71320b2db5.tar.bz2 yosys-5d16bf831688ff665b0ec2abd6835b71320b2db5.zip | |
parse_xaiger() to do "clean -purge"
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 06522939f..2e1fb8fad 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -974,7 +974,7 @@ void AigerReader::post_process() // operate (and run checks on) this one module RTLIL::Design *mapped_design = new RTLIL::Design; mapped_design->add(module); - Pass::call(mapped_design, "clean"); + Pass::call(mapped_design, "clean -purge"); mapped_design->modules_.erase(module->name); delete mapped_design; |