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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:37:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:37:01 -0700 |
| commit | 5b89553a1f1a3b3ec1667cadd34dc1939ebe67c2 (patch) | |
| tree | 30eef2ad57cc0f6a620728ed4a014846cad64039 | |
| parent | 158325956e6bf711137e6198fb88e95a1e6250b9 (diff) | |
| download | yosys-5b89553a1f1a3b3ec1667cadd34dc1939ebe67c2.tar.gz yosys-5b89553a1f1a3b3ec1667cadd34dc1939ebe67c2.tar.bz2 yosys-5b89553a1f1a3b3ec1667cadd34dc1939ebe67c2.zip | |
nullptr check
| -rw-r--r-- | passes/techmap/abc9.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f90834aa9..0312e3e1f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -124,6 +124,7 @@ void handle_loops(RTLIL::Design *design) RTLIL::SigSpec sig; for (auto b : it->second) { Wire *w = b.wire; + if (!w) continue; if (w->port_output) { log_assert(w->get_bool_attribute("\\abc_scc_break")); w = module->wire(stringf("%s.abci", w->name.c_str())); |