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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-03-13 15:00:18 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-03-13 15:00:18 +0100 |
| commit | 5b73e7c63a9f939da93dd8dca7d7b1e4c2a949ae (patch) | |
| tree | ab8b6b70840e556612240af2f589e53408764878 | |
| parent | 7c54e619799e826454820015e37ef0bc829c14a8 (diff) | |
| download | yosys-5b73e7c63a9f939da93dd8dca7d7b1e4c2a949ae.tar.gz yosys-5b73e7c63a9f939da93dd8dca7d7b1e4c2a949ae.tar.bz2 yosys-5b73e7c63a9f939da93dd8dca7d7b1e4c2a949ae.zip | |
Added back tests for logger
| -rw-r--r-- | tests/various/logger_error.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_nowarning.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warn.ys | 6 | ||||
| -rw-r--r-- | tests/various/logger_warning.ys | 6 |
4 files changed, 24 insertions, 0 deletions
diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys new file mode 100644 index 000000000..46fe7f506 --- /dev/null +++ b/tests/various/logger_error.ys @@ -0,0 +1,6 @@ +logger -werror "is implicitly declared." -expect error "is implicitly declared." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys new file mode 100644 index 000000000..87cbbc644 --- /dev/null +++ b/tests/various/logger_nowarning.ys @@ -0,0 +1,6 @@ +logger -expect-no-warnings -nowarn "is implicitly declared." +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys new file mode 100644 index 000000000..2316ae4c6 --- /dev/null +++ b/tests/various/logger_warn.ys @@ -0,0 +1,6 @@ +logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys new file mode 100644 index 000000000..642b1b97b --- /dev/null +++ b/tests/various/logger_warning.ys @@ -0,0 +1,6 @@ +logger -expect warning "is implicitly declared." 2 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF |