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| author | whitequark <whitequark@whitequark.org> | 2020-06-03 12:45:02 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-03 12:45:02 +0000 |
| commit | 577859fbdbefaabac4a3c61288264f2505261586 (patch) | |
| tree | 53d071309cc72d512d4b54ec866bb04d3c944206 | |
| parent | 4b3f48a7ec5d00395f50d46ed0222c01dee9fc09 (diff) | |
| parent | fb5b070e7e9e22b02a3ee94217c8ae20cef41f0b (diff) | |
| download | yosys-577859fbdbefaabac4a3c61288264f2505261586.tar.gz yosys-577859fbdbefaabac4a3c61288264f2505261586.tar.bz2 yosys-577859fbdbefaabac4a3c61288264f2505261586.zip | |
Merge pull request #2104 from whitequark/simplify-techmap
techmap: simplify
| -rw-r--r-- | passes/techmap/.gitignore | 1 | ||||
| -rw-r--r-- | passes/techmap/Makefile.inc | 12 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 35 |
3 files changed, 8 insertions, 40 deletions
diff --git a/passes/techmap/.gitignore b/passes/techmap/.gitignore deleted file mode 100644 index e6dcc6bc0..000000000 --- a/passes/techmap/.gitignore +++ /dev/null @@ -1 +0,0 @@ -techmap.inc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 1802ba0de..873286608 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -45,18 +45,6 @@ OBJS += passes/techmap/flowmap.o OBJS += passes/techmap/extractinv.o endif -GENFILES += passes/techmap/techmap.inc - -passes/techmap/techmap.inc: techlibs/common/techmap.v - $(Q) mkdir -p $(dir $@) - $(P) echo "// autogenerated from $<" > $@.new - $(Q) echo "static char stdcells_code[] = {" >> $@.new - $(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new - $(Q) echo "0};" >> $@.new - $(Q) mv $@.new $@ - -passes/techmap/techmap.o: passes/techmap/techmap.inc - ifeq ($(DISABLE_SPAWN),0) TARGETS += $(PROGRAM_PREFIX)yosys-filterlib$(EXE) EXTRA_OBJS += passes/techmap/filterlib.o diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 6ac1d1113..c88f7bd0a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -27,7 +27,6 @@ #include <string.h> #include "simplemap.h" -#include "passes/techmap/techmap.inc" YOSYS_NAMESPACE_BEGIN @@ -81,22 +80,12 @@ struct TechmapWorker typedef dict<IdString, std::vector<TechmapWireData>> TechmapWires; - bool extern_mode; - bool assert_mode; - bool flatten_mode; - bool recursive_mode; - bool autoproc_mode; - bool ignore_wb; - - TechmapWorker() - { - extern_mode = false; - assert_mode = false; - flatten_mode = false; - recursive_mode = false; - autoproc_mode = false; - ignore_wb = false; - } + bool extern_mode = false; + bool assert_mode = false; + bool flatten_mode = false; + bool recursive_mode = false; + bool autoproc_mode = false; + bool ignore_wb = false; std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) { @@ -279,7 +268,6 @@ struct TechmapWorker tpl_written_bits.insert(bit); SigMap port_signal_map; - SigSig port_signal_assign; for (auto &it : cell->connections()) { @@ -1282,8 +1270,7 @@ struct TechmapPass : public Pass { RTLIL::Design *map = new RTLIL::Design; if (map_files.empty()) { - std::istringstream f(stdcells_code); - Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend); + Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend); } else { for (auto &fn : map_files) if (fn.compare(0, 1, "%") == 0) { @@ -1295,13 +1282,7 @@ struct TechmapPass : public Pass { if (!map->module(mod->name)) map->add(mod->clone()); } else { - std::ifstream f; - rewrite_filename(fn); - f.open(fn.c_str()); - yosys_input_files.insert(fn); - if (f.fail()) - log_cmd_error("Can't open map file `%s'\n", fn.c_str()); - Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend)); + Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend)); } } |