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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-30 20:48:50 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-31 01:08:41 +0100 |
| commit | 56e7791760ce67cb1831691460b50bf73a4f5117 (patch) | |
| tree | add3d8b2488630378d8152b4c305ff99bd27b75f | |
| parent | 07a657fb0ca08012af3de410520458af255b1097 (diff) | |
| download | yosys-56e7791760ce67cb1831691460b50bf73a4f5117.tar.gz yosys-56e7791760ce67cb1831691460b50bf73a4f5117.tar.bz2 yosys-56e7791760ce67cb1831691460b50bf73a4f5117.zip | |
verilog backend: Emit a `wire` for ports as well.
Fixes #3177.
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 32003cf54..aa1d4558c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -432,7 +432,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) dump_const(f, wire->attributes.at(ID::init)); } f << stringf(";\n"); - } else if (!wire->port_input && !wire->port_output) + } else f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); #endif } |