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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-10 11:38:50 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-10 11:38:50 +0200 |
| commit | 545a3417c81d454071b8d39b6ac88258ceb891a3 (patch) | |
| tree | 768fbdc3247afadcf3cb6c6844dc9cac1f9a9a42 | |
| parent | 51f67e55f257e905bc7589a7f529efcd191172f4 (diff) | |
| download | yosys-545a3417c81d454071b8d39b6ac88258ceb891a3.tar.gz yosys-545a3417c81d454071b8d39b6ac88258ceb891a3.tar.bz2 yosys-545a3417c81d454071b8d39b6ac88258ceb891a3.zip | |
resetall does not affect text defines, but undefineall does
| -rw-r--r-- | frontends/verilog/preproc.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 883531e78..9781a22d9 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -961,6 +961,10 @@ frontend_verilog_preproc(std::istream &f, } if (tok == "`resetall") { + continue; + } + + if (tok == "`undefineall" && sv_mode) { defines.clear(); global_defines_cache.clear(); continue; |