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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 15:46:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 15:46:15 -0700 |
| commit | 5344bfe637e0c8d527f94f615e4ed8704c358cf8 (patch) | |
| tree | 486f270ce65ee04eccabc44e1514fbe883816e13 | |
| parent | 74eac766995237dec86d51778811cf186c68d851 (diff) | |
| download | yosys-5344bfe637e0c8d527f94f615e4ed8704c358cf8.tar.gz yosys-5344bfe637e0c8d527f94f615e4ed8704c358cf8.tar.bz2 yosys-5344bfe637e0c8d527f94f615e4ed8704c358cf8.zip | |
Perform D replacement properly
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 13 | ||||
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 5 |
2 files changed, 11 insertions, 7 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 547073aa6..ba8a1de05 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -144,13 +144,22 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) cell->setParam("\\BREG", 1); } if (st.ffD) { + SigSpec D_ = cell->getPort("\\D"); + SigSpec D = st.ffB->getPort("\\D"); + SigSpec Q = st.ffB->getPort("\\Q"); + D_.replace(Q, D); + if (st.ffDmux) { + SigSpec Y = st.ffDmux->getPort("\\Y"); + SigSpec AB = st.ffDmux->getPort(st.ffDenpol ? "\\B" : "\\A"); SigSpec S = st.ffDmux->getPort("\\S"); - cell->setPort("\\CED", st.ffBenpol ? S : pm.module->Not(NEW_ID, S)); + D_.replace(Y, AB); + + cell->setPort("\\CED", st.ffDenpol ? S : pm.module->Not(NEW_ID, S)); } else cell->setPort("\\CED", State::S1); - cell->setPort("\\D", st.sigD); + cell->setPort("\\D", D_); cell->setParam("\\DREG", 1); } diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 6cc42e2e1..9e4738c88 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -286,11 +286,6 @@ match ffDmux optional endmatch -code sigD - if (ffDmux) - sigD.replace(port(ffDmux, \Y), port(ffDmux, ffDenpol ? \B : \A)); -endcode - match ffMmux if param(dsp, \MREG).as_int() == 0 if nusers(sigM) == 2 |