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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 14:37:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 14:37:20 -0700 |
| commit | 523e7ee7828326a0b89a1ed9fdd2eb717ef1815a (patch) | |
| tree | d2a801ae37c5d14f74fd88f301ec7e4f7f76c1b6 | |
| parent | f433a523742350b4bb9291ad65299015e2c81f05 (diff) | |
| parent | e581a3e6f4c8763c6a308d1330dbf1ee4bb19499 (diff) | |
| download | yosys-523e7ee7828326a0b89a1ed9fdd2eb717ef1815a.tar.gz yosys-523e7ee7828326a0b89a1ed9fdd2eb717ef1815a.tar.bz2 yosys-523e7ee7828326a0b89a1ed9fdd2eb717ef1815a.zip | |
Merge branch 'xc7mux' into xc7mux_wip
| -rw-r--r-- | backends/aiger/xaiger.cc | 14 | ||||
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 7 | ||||
| -rwxr-xr-x | tests/tools/autotest.sh | 1 |
3 files changed, 15 insertions, 7 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 48e902666..637c54ff9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -86,14 +86,15 @@ struct XAigerWriter int bit2aig(SigBit bit) { - // NB: Cannot use iterator returned from aig_map.insert() - // since this function is called recursively auto it = aig_map.find(bit); if (it != aig_map.end()) { log_assert(it->second >= 0); return it->second; } + // NB: Cannot use iterator returned from aig_map.insert() + // since this function is called recursively + int a = -1; if (not_map.count(bit)) { a = bit2aig(not_map.at(bit)) ^ 1; @@ -109,7 +110,7 @@ struct XAigerWriter } if (bit == State::Sx || bit == State::Sz) { - log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit)); + log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n"); a = aig_map.at(State::S0); } @@ -428,12 +429,13 @@ struct XAigerWriter module->connect(new_bit, bit); if (not_map.count(bit)) not_map[new_bit] = not_map.at(bit); - else if (and_map.count(bit)) - and_map[new_bit] = and_map.at(bit); + else if (and_map.count(bit)) { + //and_map[new_bit] = and_map.at(bit); // Breaks gcc-4.8 + and_map.insert(std::make_pair(new_bit, and_map.at(bit))); + } else if (alias_map.count(bit)) alias_map[new_bit] = alias_map.at(bit); else - //log_abort(); alias_map[new_bit] = bit; output_bits.erase(bit); output_bits.insert(new_bit); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d50a38b7a..5f236992d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -114,13 +114,20 @@ struct ConstEvalAig RTLIL::Cell *cell = sig2driver.at(output); RTLIL::SigBit sig_a = cell->getPort("\\A"); + sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation + // that may occur does so here, and + // not mid insertion (below) sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end()); if (!inputs.count(sig_a)) compute_deps(sig_a, inputs); if (cell->type == "$_AND_") { RTLIL::SigSpec sig_b = cell->getPort("\\B"); + sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation + // that may occur does so here, and + // not mid insertion (below) sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end()); + if (!inputs.count(sig_b)) compute_deps(sig_b, inputs); } diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index d90abf848..96d9cdda9 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -226,7 +226,6 @@ do if $warn_iverilog_git; then echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." fi - cat ${bn}.err $keeprunning || exit 1 fi done |