diff options
| author | Anonymous Maarten <anonymous.maarten@gmail.com> | 2020-06-17 13:52:45 +0200 |
|---|---|---|
| committer | Anonymous Maarten <anonymous.maarten@gmail.com> | 2020-06-17 15:10:08 +0200 |
| commit | 504f22061995d5b0ad6549e360ee1dded0e86116 (patch) | |
| tree | 4a7bc07bb34e94ecf82930e040795ed27328bb9d | |
| parent | 35008e6d40af212655b549f481f58f9c066be08a (diff) | |
| download | yosys-504f22061995d5b0ad6549e360ee1dded0e86116.tar.gz yosys-504f22061995d5b0ad6549e360ee1dded0e86116.tar.bz2 yosys-504f22061995d5b0ad6549e360ee1dded0e86116.zip | |
MSVC does not understand __builtin_unreachable
| -rw-r--r-- | frontends/verilog/preproc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7905ea598..ea23139e2 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -591,7 +591,7 @@ read_define_args() default: // The only FSM states are 0-2 and we dealt with 2 at the start of the loop. - __builtin_unreachable(); + log_assert(false); } } |