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author | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 12:22:03 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 12:22:03 -0700 |
commit | 4fb9ccfcd81db6d2e574bea3d142b714126d1123 (patch) | |
tree | ef8e6ccb8310c4e1dfc6780bb15750425fcbfb83 | |
parent | 42c33db22caeffa05bde59d915a4433b756929a1 (diff) | |
download | yosys-4fb9ccfcd81db6d2e574bea3d142b714126d1123.tar.gz yosys-4fb9ccfcd81db6d2e574bea3d142b714126d1123.tar.bz2 yosys-4fb9ccfcd81db6d2e574bea3d142b714126d1123.zip |
synth_ice40 to use renamed files
-rw-r--r-- | techlibs/ice40/synth_ice40.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 3faa10b4f..91cd063a2 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -317,9 +317,9 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { - run("read_verilog +/ice40/cells_box.v"); + run("read_verilog +/ice40/abc.v"); run("techmap -map +/techmap.v A:abc_box_id"); - run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)"); + run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)"); run("blackbox A:abc_box_id"); } else |