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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-22 08:13:09 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-22 08:13:09 +0200 |
| commit | 4b8200eb4943dcbdb2bede8695ca77cd7d6fde3a (patch) | |
| tree | a5410bccd83907f251bd307ad631111863e8b8a8 | |
| parent | 405cf67b6479f0a18d4405a98493e5b801d3b926 (diff) | |
| download | yosys-4b8200eb4943dcbdb2bede8695ca77cd7d6fde3a.tar.gz yosys-4b8200eb4943dcbdb2bede8695ca77cd7d6fde3a.tar.bz2 yosys-4b8200eb4943dcbdb2bede8695ca77cd7d6fde3a.zip | |
Fixed segfault on invalid verilog constant 1'b_
| -rw-r--r-- | frontends/verilog/const2ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 9cc99750f..4a58357bf 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -122,7 +122,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le } int len = GetSize(data); - RTLIL::State msb = data.back(); + RTLIL::State msb = data.empty() ? RTLIL::S0 : data.back(); if (len_in_bits < 0) { if (len < 32) |