diff options
| author | Jannis Harder <me@jix.one> | 2022-08-05 15:34:14 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-08-16 13:37:30 +0200 |
| commit | 4ad13c647e2789268aed06d528bc2a40c6196133 (patch) | |
| tree | 40eea3ca35c263a7ffa37706fe0ded6639cd62b8 | |
| parent | 65145db7e7bec998a194aa0f6335de50df00e550 (diff) | |
| download | yosys-4ad13c647e2789268aed06d528bc2a40c6196133.tar.gz yosys-4ad13c647e2789268aed06d528bc2a40c6196133.tar.bz2 yosys-4ad13c647e2789268aed06d528bc2a40c6196133.zip | |
clk2fflogic: Generate less unused logic when using verific
Verific generates a lot of FFs with an unused async load and we cannot
always optimize that away before running clk2fflogic, so check for that
special case here.
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index b1b0567a0..2384ffced 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -233,7 +233,10 @@ struct Clk2fflogicPass : public Pass { qval = past_q; } - if (ff.has_aload) { + // The check for a constant sig_aload is also done by opt_dff, but when using verific and running + // clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids + // generating a lot of extra logic. + if (ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1)) { SigSpec sig_aload = wrap_async_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine, NEW_ID); if (!ff.is_fine) |