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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-21 15:01:13 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-21 15:01:13 +0100 |
| commit | 49dd9c713f008173100e159782223aede631b510 (patch) | |
| tree | 751e8b2397a4b01b9d301eefe5b56de818e5ca13 | |
| parent | 1f6737f08f812f01e3917389e1fee5a37bd446b6 (diff) | |
| download | yosys-49dd9c713f008173100e159782223aede631b510.tar.gz yosys-49dd9c713f008173100e159782223aede631b510.tar.bz2 yosys-49dd9c713f008173100e159782223aede631b510.zip | |
Fixed "flatten" for non-pre-derived modules
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8435d3a32..87e736bda 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1088,7 +1088,7 @@ struct FlattenPass : public Pass { if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, false)) did_something = true; } else { - for (auto mod : design->modules()) + for (auto mod : vector<Module*>(design->modules())) if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) did_something = true; } @@ -1098,7 +1098,7 @@ struct FlattenPass : public Pass { if (top_mod != NULL) { dict<RTLIL::IdString, RTLIL::Module*> new_modules; - for (auto mod : design->modules()) + for (auto mod : vector<Module*>(design->modules())) if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) { new_modules[mod->name] = mod; } else { |