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| author | Lloyd Parkes <lloyd@must-have-coffee.gen.nz> | 2022-10-23 11:02:18 +1300 |
|---|---|---|
| committer | Lloyd Parkes <lloyd@must-have-coffee.gen.nz> | 2022-10-23 11:02:18 +1300 |
| commit | 49945ab1c29482344a36c17eefde44243de90972 (patch) | |
| tree | d87759009f1a887d1dd96e329732c4f0f75bdcda | |
| parent | 32808b26c617415edde79eda97c71dcb1c9b6630 (diff) | |
| download | yosys-49945ab1c29482344a36c17eefde44243de90972.tar.gz yosys-49945ab1c29482344a36c17eefde44243de90972.tar.bz2 yosys-49945ab1c29482344a36c17eefde44243de90972.zip | |
Replace GNU specific invocation of basename(1) with the equivalent
POSIX one. The tests now complete on BSD as well as GNU/Linux.
| -rwxr-xr-x | tests/sim/run-test.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sim/run-test.sh b/tests/sim/run-test.sh index d34d1f3c9..a5120e77e 100755 --- a/tests/sim/run-test.sh +++ b/tests/sim/run-test.sh @@ -3,7 +3,7 @@ set -eu source ../gen-tests-makefile.sh echo "Generate FST for sim models" find tb/* -name tb*.v | while read name; do - test_name=$(basename -s .v $name) + test_name=$(basename $name .v) echo "Test $test_name" verilog_name=${test_name:3}.v iverilog -o tb/$test_name.out $name $verilog_name |