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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 22:25:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 22:25:22 -0800 |
| commit | 45d49d5d14b64cce77e667e99c2579237638bedf (patch) | |
| tree | 550ae58621248c008d75d29a1e7166bb297ec6c4 | |
| parent | 82459c16c482ad9115c742d726fd1f46527a3bab (diff) | |
| download | yosys-45d49d5d14b64cce77e667e99c2579237638bedf.tar.gz yosys-45d49d5d14b64cce77e667e99c2579237638bedf.tar.bz2 yosys-45d49d5d14b64cce77e667e99c2579237638bedf.zip | |
Get rid of debugging stuff in abc9
| -rw-r--r-- | passes/techmap/abc9.cc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f684ad8de..5c10278a9 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -411,9 +411,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design, module); - Pass::call(design, "write_verilog -norename -noexpr input.v"); Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); - Pass::call(design, stringf("write_xaiger -ascii -symbols %s/input.xaag; read_aiger -wideports %s/input.xaag; write_verilog -norename -noexpr input.v", tempdir_name.c_str(), tempdir_name.c_str())); // Now 'unexpose' those wires by undoing // the expose operation -- remove them from PO/PI @@ -843,7 +841,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri wire = module->wire(r.first); log_assert(wire); int i = r.second; - printf("%s %s %d\n", w->name.c_str(), wire->name.c_str(), i); signal = RTLIL::SigSpec(wire, i); } log_assert(GetSize(signal) >= GetSize(remap_wire)); @@ -854,13 +851,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri conn.second = signal; in_wires++; module->connect(conn); - printf("INPUT: assign %s = %s\n", remap_wire->name.c_str(), wire->name.c_str()); } else if (w->port_output) { RTLIL::SigSig conn; conn.first = signal; conn.second = remap_wire; - printf("OUTPUT: assign %s = %s\n", wire->name.c_str(), remap_wire->name.c_str()); out_wires++; module->connect(conn); } @@ -1084,7 +1079,7 @@ struct Abc9Pass : public Pass { std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; - show_tempdir = true; cleanup = false; + show_tempdir = true; cleanup = true; vector<int> lut_costs; markgroups = false; |