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author | Clifford Wolf <clifford@clifford.at> | 2014-10-16 00:54:14 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-10-16 00:54:14 +0200 |
commit | 3be5fa053f61a29039ed99876d3e89406c99cb7d (patch) | |
tree | 9bcdc2cbdae20e19ee7f74bacdb6a62c2c0705a7 | |
parent | 6b05a9e8075af923c67ec3bb1b74573294ac8838 (diff) | |
download | yosys-3be5fa053f61a29039ed99876d3e89406c99cb7d.tar.gz yosys-3be5fa053f61a29039ed99876d3e89406c99cb7d.tar.bz2 yosys-3be5fa053f61a29039ed99876d3e89406c99cb7d.zip |
Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects
-rw-r--r-- | kernel/rtlil.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 28f0dfdc5..5a94008d8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2980,7 +2980,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); if (index_tokens.size() == 1) { cover("kernel.rtlil.sigspec.parse.bit_sel"); - sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str()))); + int a = atoi(index_tokens.at(0).c_str()); + if (a < 0 || a >= wire->width) + return false; + sig.append(RTLIL::SigSpec(wire, a)); } else { cover("kernel.rtlil.sigspec.parse.part_sel"); int a = atoi(index_tokens.at(0).c_str()); @@ -2989,6 +2992,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri int tmp = a; a = b, b = tmp; } + if (a < 0 || a >= wire->width) + return false; + if (b < 0 || b >= wire->width) + return false; sig.append(RTLIL::SigSpec(wire, a, b-a+1)); } } else |