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| author | Lukasz Dalek <ldalek@antmicro.com> | 2020-05-19 16:58:48 +0200 |
|---|---|---|
| committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-24 11:57:45 +0200 |
| commit | 3b81a1b80926138cf0c3fe6d88818b689be3121c (patch) | |
| tree | bd603d80da1343ef796c97c69e610bd6c73c568b | |
| parent | 0835a86e30fc2a934f5e6c96b28c90b59654ed92 (diff) | |
| download | yosys-3b81a1b80926138cf0c3fe6d88818b689be3121c.tar.gz yosys-3b81a1b80926138cf0c3fe6d88818b689be3121c.tar.bz2 yosys-3b81a1b80926138cf0c3fe6d88818b689be3121c.zip | |
Support optional labels at the end of module definition
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 15c231f3b..6687a195e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -435,7 +435,7 @@ module: mod->str = *$4; append_attr(mod, $1); delete $4; - } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE { + } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label { if (port_stubs.size() != 0) frontend_verilog_yyerror("Missing details for module port `%s'.", port_stubs.begin()->first.c_str()); |