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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 17:10:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 17:10:43 -0700 |
| commit | 3a390733027584071d0cd3b2d99c738ce6f1a829 (patch) | |
| tree | 89b8dd1c29959dc6b744a4675c3e1c91a38b7507 | |
| parent | a1123b095c54adb3a700aa33f98edf1dcee12ac2 (diff) | |
| download | yosys-3a390733027584071d0cd3b2d99c738ce6f1a829.tar.gz yosys-3a390733027584071d0cd3b2d99c738ce6f1a829.tar.bz2 yosys-3a390733027584071d0cd3b2d99c738ce6f1a829.zip | |
Set more ports explicitly
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index ae8cd64da..e0c7823ed 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -44,6 +44,8 @@ static Cell* addDsp(Module *module) { cell->setParam("\\OPMODEREG", 0); cell->setParam("\\PREG", 0); cell->setParam("\\USE_MULT", Const("NONE")); + cell->setParam("\\USE_SIMD", Const("ONE48")); + cell->setParam("\\USE_DPORT", Const("FALSE")); cell->setPort("\\D", Const(0, 24)); cell->setPort("\\INMODE", Const(0, 5)); diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index cc37f0085..8901b215b 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -25,7 +25,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .OPMODEREG(0), .PREG(0), .USE_MULT("MULTIPLY"), - .USE_SIMD("ONE48") + .USE_SIMD("ONE48"), + .USE_DPORT("FALSE") ) _TECHMAP_REPLACE_ ( //Data path .A({{5{A[24]}}, A}), |