diff options
| author | Jannis Harder <me@jix.one> | 2022-10-24 16:12:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-24 16:12:52 +0200 |
| commit | 3a37597e9f3cbcd69a28663933074c24d5c03feb (patch) | |
| tree | 789dbdf705fd6641da294cad8d6b655285b764b1 | |
| parent | 9f76ff0b6a6892db2761964aec10ccf442f174d6 (diff) | |
| parent | 0f96ae599037a945967070211676e32d6e50714d (diff) | |
| download | yosys-3a37597e9f3cbcd69a28663933074c24d5c03feb.tar.gz yosys-3a37597e9f3cbcd69a28663933074c24d5c03feb.tar.bz2 yosys-3a37597e9f3cbcd69a28663933074c24d5c03feb.zip | |
Merge pull request #3518 from jix/smtmap
Add smtmap.v describing the smt2 backend's behavior for undef bits
| -rw-r--r-- | techlibs/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | techlibs/common/smtmap.v | 28 |
2 files changed, 29 insertions, 0 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 607e772a2..47f1ed604 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -22,6 +22,7 @@ kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help $(eval $(call add_share_file,share,techlibs/common/simlib.v)) $(eval $(call add_share_file,share,techlibs/common/simcells.v)) $(eval $(call add_share_file,share,techlibs/common/techmap.v)) +$(eval $(call add_share_file,share,techlibs/common/smtmap.v)) $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v)) $(eval $(call add_share_file,share,techlibs/common/adff2dff.v)) $(eval $(call add_share_file,share,techlibs/common/dff2ff.v)) diff --git a/techlibs/common/smtmap.v b/techlibs/common/smtmap.v new file mode 100644 index 000000000..8c7503dc8 --- /dev/null +++ b/techlibs/common/smtmap.v @@ -0,0 +1,28 @@ +(* techmap_celltype = "$pmux" *) +module smt_pmux (A, B, S, Y); + parameter WIDTH = 1; + parameter S_WIDTH = 1; + + (* force_downto *) + input [WIDTH-1:0] A; + (* force_downto *) + input [WIDTH*S_WIDTH-1:0] B; + (* force_downto *) + input [S_WIDTH-1:0] S; + (* force_downto *) + output [WIDTH-1:0] Y; + + (* force_downto *) + wire [WIDTH-1:0] Y_B; + + genvar i, j; + generate + (* force_downto *) + wire [WIDTH*(S_WIDTH+1)-1:0] C; + + assign C[WIDTH-1:0] = A; + for (i = 0; i < S_WIDTH; i = i + 1) + assign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i]; + assign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH]; + endgenerate +endmodule |