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| author | N. Engelhardt <nak@symbioticeda.com> | 2020-06-16 12:31:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-16 12:31:34 +0200 |
| commit | 39ba90a8b84d740b670a9f1df5148b824d441c63 (patch) | |
| tree | 489e8be937950e97a21d769f8a7240ab131a2cc1 | |
| parent | 334ec5fa0a90b1816060c67bff72362cbd6483c7 (diff) | |
| parent | 9509444ef2a55dcd75a6f5e1d96337f442238cee (diff) | |
| download | yosys-39ba90a8b84d740b670a9f1df5148b824d441c63.tar.gz yosys-39ba90a8b84d740b670a9f1df5148b824d441c63.tar.bz2 yosys-39ba90a8b84d740b670a9f1df5148b824d441c63.zip | |
Merge pull request #2156 from XarkLabs/master
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index ad572c877..7ee809262 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2508,7 +2508,7 @@ module SB_SPRAM256KA ( always @(negedge POWEROFF) begin for (i = 0; i <= 16383; i = i+1) - mem[i] = 'bx; + mem[i] = 16'bx; end always @(posedge CLOCK, posedge off) begin @@ -2516,17 +2516,17 @@ module SB_SPRAM256KA ( DATAOUT <= 0; end else if (STANDBY) begin - DATAOUT <= 'bx; + DATAOUT <= 16'bx; end else if (CHIPSELECT) begin if (!WREN) begin DATAOUT <= mem[ADDRESS]; end else begin - if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0]; - if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4]; - if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8]; - if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12]; - DATAOUT <= 'bx; + if (MASKWREN[0]) mem[ADDRESS][ 3: 0] <= DATAIN[ 3: 0]; + if (MASKWREN[1]) mem[ADDRESS][ 7: 4] <= DATAIN[ 7: 4]; + if (MASKWREN[2]) mem[ADDRESS][11: 8] <= DATAIN[11: 8]; + if (MASKWREN[3]) mem[ADDRESS][15:12] <= DATAIN[15:12]; + DATAOUT <= 16'bx; end end end |