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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 17:08:32 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 17:08:32 -0800 |
| commit | 396da54b5297e644087c63cd7bfb244e7ae81e3a (patch) | |
| tree | 9dfcecb5f5991c32d614e817dd39e30a08f63f4a | |
| parent | 206f11dca3210931c542fb010f525949f1246540 (diff) | |
| download | yosys-396da54b5297e644087c63cd7bfb244e7ae81e3a.tar.gz yosys-396da54b5297e644087c63cd7bfb244e7ae81e3a.tar.bz2 yosys-396da54b5297e644087c63cd7bfb244e7ae81e3a.zip | |
Use module->addLut()
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 62354498c..931d2fd36 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -227,11 +227,7 @@ void AigerReader::parse_xaiger() RTLIL::Cell *output_cell = module->cell(stringf("\\n%d_and", rootNodeID)); log_assert(output_cell); module->remove(output_cell); - RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); - cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); - cell->parameters["\\LUT"] = std::move(lut_mask); - cell->setPort("\\A", input_sig); - cell->setPort("\\Y", output_sig); + module->addLut(NEW_ID, input_sig, output_sig, std::move(lut_mask)); } } else if (c == 'n') { |