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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 20:56:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 20:56:13 -0700 |
| commit | 37a34eeb0438261f432917fb5d60a5320f56a8de (patch) | |
| tree | f560c0e0a93e754014922ba36ed1f2692db320bf | |
| parent | af147d14300a8fbff2db8d823cf3622ec5a81ca6 (diff) | |
| download | yosys-37a34eeb0438261f432917fb5d60a5320f56a8de.tar.gz yosys-37a34eeb0438261f432917fb5d60a5320f56a8de.tar.bz2 yosys-37a34eeb0438261f432917fb5d60a5320f56a8de.zip | |
Fix RSTP
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index fe82b1307..055b3d6aa 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -438,7 +438,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) st.ffPrstmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); } else - cell->setPort("\\RSTP", State::S1); + cell->setPort("\\RSTP", State::S0); if (st.ffPcemux) { SigSpec S = st.ffPcemux->getPort("\\S"); cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S)); |