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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 12:39:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 12:39:22 -0700 |
| commit | 2f863660870e9ef66c5fcccbf711cf9eb46849c0 (patch) | |
| tree | fa0cfbd0306eb79fe4b626b61a15f057a4edcc52 | |
| parent | 91687d3feae8df0e315232d3989a445e7d452d1f (diff) | |
| download | yosys-2f863660870e9ef66c5fcccbf711cf9eb46849c0.tar.gz yosys-2f863660870e9ef66c5fcccbf711cf9eb46849c0.tar.bz2 yosys-2f863660870e9ef66c5fcccbf711cf9eb46849c0.zip | |
Add reference to source of Tclktoq timing
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 66d9573d3..36e1a08e4 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -20,6 +20,8 @@ // ============================================================================ +// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 + module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; |