diff options
| author | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-10 19:50:02 +0100 |
|---|---|---|
| committer | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-10 19:50:02 +0100 |
| commit | 2f2e76ac68dc8da8618ebbf602e2c871f5d4b1b8 (patch) | |
| tree | 88e8f371fe677c8bb3093190c772b43472c66d36 | |
| parent | 63ca8d3fe4273d9e07233f94037a63659d6d18e4 (diff) | |
| download | yosys-2f2e76ac68dc8da8618ebbf602e2c871f5d4b1b8.tar.gz yosys-2f2e76ac68dc8da8618ebbf602e2c871f5d4b1b8.tar.bz2 yosys-2f2e76ac68dc8da8618ebbf602e2c871f5d4b1b8.zip | |
- frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc/abc.cc: #include <climits> for PATH_MAX.
| -rw-r--r-- | frontends/vhdl2verilog/vhdl2verilog.cc | 1 | ||||
| -rw-r--r-- | passes/abc/abc.cc | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index d8568fe94..83035d329 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -27,6 +27,7 @@ #include <string.h> #include <dirent.h> #include <errno.h> +#include <limits.h> struct Vhdl2verilogPass : public Pass { Vhdl2verilogPass() : Pass("vhdl2verilog", "importing VHDL designs using vhdl2verilog") { } diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 24a634f65..286b750cc 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -45,6 +45,7 @@ #include <dirent.h> #include <cerrno> #include <sstream> +#include <climits> #include "blifparse.h" |